Changelog

new FPGA.bit: clock mode 3 inverted MOSI instead of Clock line

Bugfix (temp): set minimal SPI baudrate to 330000

Bugfix: configure and set DIOs only once at startup instead of every time a connection is opened

Bugfix: GetGlobals set polarity to on

program FPGA just once on start-up instead of every time a connection is established (saves about 1 second per connection)

enabled compiler optimisations

switched from CommonLib to libAnaGate und libAnaGateExt

I2C: detect and process Arbitration Lost

SPI: added more performant asymmetric Transceive implementation

SPI: added Sequence command

Initial version, based on Firmware AnaGate UP 1.3.3